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System and method for dynamic pipelining of direct memory access (DMA) transactions

机译:动态流水线直接内存访问(DMA)事务的系统和方法

摘要

A method and a system for pipelining read transactions of a host computer from a storage module, including: transferring from a host computer to an accelerator a read list, including at least one pointer to a data block stored on the storage module, and a respective data block size; sending an acknowledgement to the host; fetching at least one data block by the accelerator from the storage module, and writing it to a staging buffer in a sequential order; sending at least one read request from the host computer to the accelerator, relating to at least one requested data block. If the data block is available on the staging buffer, then sending the corresponding data to the host from the staging buffer. Otherwise the read response is delayed until the requested data is fetched from the storage module.
机译:一种用于对来自存储模块的主机的读取事务进行流水线传输的方法和系统,包括:从主机向加速器传输读取列表,包括至少一个指向存储模块中存储的数据块的指针,以及相应的数据块大小;向主机发送确认;加速器从存储模块中提取至少一个数据块,并将其按顺序写入分段缓冲区;从主机向加速器发送至少一个与至少一个请求的数据块有关的读取请求。如果数据块在登台缓冲区上可用,则将相应的数据从登台缓冲区发送到主机。否则,读取响应将延迟,直到从存储模块中提取请求的数据为止。

著录项

  • 公开/公告号US10552349B1

    专利类型

  • 公开/公告日2020-02-04

    原文格式PDF

  • 申请/专利权人 LIGHTBITS LABS LTD.;

    申请/专利号US201816008084

  • 发明设计人 AMIR SHAVIT;ROY GERON;

    申请日2018-06-14

  • 分类号G06F13/36;G06F13/16;G06F13/28;

  • 国家 US

  • 入库时间 2022-08-21 11:24:58

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