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PERIPHERAL BASED MEMORY SAFETY SCHEME FOR MULTI-CORE PLATFORMS
PERIPHERAL BASED MEMORY SAFETY SCHEME FOR MULTI-CORE PLATFORMS
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机译:多核平台的基于外围的内存安全方案
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摘要
A computing system using low-fat pointers, including: a memory configured to be accessed by the low-fat pointers; a processing core configured to access the memory; an interrupt controller configured to receive interrupts and to communicate interrupts to processes running on the processing core; and a memory safety peripheral configured to receive a pointer request, wherein the pointer is a low-fat pointer and to verify that the pointer request is within required memory bounds
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