FAIL-SAFE COUNTER EVALUATOR TO INSURE PROPER COUNTING BY A COUNTER

摘要

A fail-safe counter evaluator (200) is provided to insure proper counting operations by fail-safe counters. The failsafe counter evaluator comprises a first microprocessor (205-1), a first counter (212-1), a second counter (212-2), a second microprocessor (205-2) and a test channel (210-2, 210-4). The first counter (212-1) is configured as a counter in operation and disposed in the first microprocessor to receive externally generated count pulses (210-1). The second counter (212-2) is disposed in the first microprocessor and configured to undergo a test (210-2: test channnel). The test channel (210-2) is configured to send an input test signal to the second counter based on test pulses (215-4: active test pulses) from the second microprocessor. The first microprocessor and the second microprocessor are synchronized (217) so that to coordinate a start and an end of the test. The second counter is evaluated after the test pulses have been sent to determine if the second counter is operating properly.