SINGLE CHIP ONU OF FPGA TRANSCEIVER FACING MULTI-APPLICATION PON

摘要

A single chip ONU of an FPGA transceiver which faces a multi-application PON, comprising: an MAC module, a physical interface module and a transceiver module, the MAC module carrying out frame forming processing in a transmission direction, adding a preamble and check sum to a data packet to be transmitted of a user, transmitting same to the physical interface module so as to carry out character set conversion according to a line coding format, burst caching, and transmitting the packet to the transceiver module for parallel-to-serial conversion; in a receiving direction, performing serial-to-parallel conversion on the received data by means of the transceiver module, transmitting same to the physical interface module for data realignment and control character deletion, and transmitting the data to the MAC module to filter and parse valid data. In the described ONU, a general layered model which use transceivers as a basis and a provided physical interface layer complete unified compatibility of transceivers having different line coding schemes and differing synchronization functions; by using the physical interface layer to shield the differences between high-speed transceivers, transceivers which have different coding formats and synchronization functions are made compatible.