An FPGA chip and an electronic device having said FPGA chip, the FPGA chip comprising: an internal memory unit (1), the internal memory unit (1) comprising a data write interface (11), and the internal memory unit (1) having multiple memory sub-cells (12), each memory sub-cell (12) comprising an enable terminal (121); and a resource management module (2), the resource management module (2) being electrically coupled to the data write interface (11) and electrically coupled to the enable terminal (121) of each memory cell (12); the resource management module (2) being capable of acquiring a current use state of an electronic device via the data write interface (11), and according to the current use state of the electronic device, outputting a first enable signal, so as to trigger enabling of one or more memory sub-cells (12) in the internal memory unit (1). The present FPGA chip has functionality of dynamic application of internal memory resources, ensuring that a minimum of internal memory resources are used in every scenario, minimizing FPGA chip power consumption.
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