首页> 外国专利> PROCESS AND METHOD FOR ACHIEVING HIGH IMMUNITY TO ULTRAFAST HIGH VOLTAGE TRANSIENTS ACROSS INORGANIC GALVANIC ISOLATION BARRIERS

PROCESS AND METHOD FOR ACHIEVING HIGH IMMUNITY TO ULTRAFAST HIGH VOLTAGE TRANSIENTS ACROSS INORGANIC GALVANIC ISOLATION BARRIERS

机译:跨有机电流隔离栅实现超高电压瞬态高抗扰度的过程和方法

摘要

A microelectronic device (100) contains a high voltage component (104) having an upper plate (132) and a lower plate (130). The upper plate is isolated from the lower plate by a main dielectric (136) between the upper plate and low voltage elements (106) at a surface of the substrate (102) of the microelectronic device. A lower-bandgap dielectric layer (140) is disposed between the upper plate and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer (144) of silicon nitride having a refractive index between 2.11 and 2.23. The lower-bandgap dielectric layer extends beyond the upper plate continuously around the upper plate. The lower-bandgap dielectric layer has an isolation break (150) surrounding the upper plate at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the upper plate.
机译:微电子器件(100)包含具有上板(132)和下板(130)的高压组件(104)。上板通过在微电子器件的衬底(102)的表面上的上板与低压元件(106)之间的主电介质(136)与下板隔离。下带隙电介质层(140)设置在上板和主电介质之间。下带隙电介质层包含折射率在2.11和2.23之间的氮化硅的至少一个子层(144)。带隙较低的介电层围绕上板连续地延伸超过上板。下带隙电介质层具有围绕上板的隔离断点(150),其距离下带隙电介质层的厚度至少是上板的厚度的两倍。

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