Peak Power Level and Back-Off Power Level An amplifier arrangement is provided for optimizing efficiency. The amplifier arrangement comprises an input power divider for dividing an input signal into a first signal having a power P m and a second signal having a power P a , a main transistor operating in a Class-B like mode receiving a first signal, and a second Auxiliary transistors that operate in Class-C mode to receive signals are included. The received first and second signals have a phase offset value Where is to be. The amplifier arrangement further includes a coupling network. Circuit element values, power P m and power P a , phase offset values of the combined network Bias condition of the auxiliary transistor; And the relative magnitude S aux of the auxiliary transistor is a predetermined back-off power level. , Based on the current scaling factor r c of the auxiliary transistor, the main transistor enlargement factor r o, m , and the auxiliary transistor enlargement factor r o, a , where And to be. Also provided is a method for determining characteristics for an amplifier arrangement.
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机译：峰值功率电平和退避功率电平提供了一个放大器装置以优化效率。该放大器装置包括输入功率分配器，该输入功率分配器用于将输入信号划分为具有功率P m 的 a 第一信号和具有 a 功率的第二信号。 P a 包括以类B模式工作的主晶体管，其接收第一信号，以及以类C模式工作以接收信号的第二辅助晶体管。所接收的第一和第二信号具有将要为的相位偏移值。放大器装置还包括耦合网络。电路元件值，功率P m 和功率P a ，组合网络的相位偏移值辅助晶体管的偏置条件;辅助晶体管的相对大小S aux 是预定的补偿功率电平。 ，基于辅助晶体管的电流比例因子r c ，主晶体管放大因子r o，m 和辅助晶体管放大因子r o， a ，然后是And。还提供了一种用于确定放大器装置的特性的方法。
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