Semiconductor package test system suitable for parallel test and test method using the same

摘要

The present invention relates to a semiconductor test, and more particularly, to a semiconductor package test system suitable for parallel testing capable of increasing the number of semiconductor devices to be tested in the test phase of the semiconductor package and a test method using the same. In order to achieve the above object, a semiconductor package test system suitable for parallel testing according to the present invention accommodates an automatic test equipment (ATE); a semiconductor package (Device Under Test: DUT), and the received semiconductor package is An interface board to be electrically connected to an automatic test device (ATE), so that a test pattern signal generated from the automatic test device (ATE) is applied to the semiconductor package; And a test handler for automatically supplying the semiconductor package (Device Under Test: DUT) to the automatic test device and transferring the semiconductor package according to the test result of the automatic test device, wherein the interface board interfaces with the router. It is based on a network-on-chip (NOC) equipped with a plurality of interconnected semiconductor packages, and by generating and forwarding a new response packet that accumulates each test result in a router on the packet response transmission path of the network-on-chip. Resolve bottlenecks.