CNN RNN Heterogenous Processor Architecture to Integrate CNN and RNN Neural Networks on a Single Chip

摘要

According to the heterogeneous processor structure in which CNN and RNN of the present invention are integrated into one high-performance low-power chip, the input partitioning form is adjusted to reduce the number of data bits required for activation of the CNN and minimize external memory access. By using a multiplication table based on a clustering table, external memory access to RNN weighting parameters is minimized, and power efficiency and area efficiency of an operator are maximized to process both CNN and RNN with high energy efficiency in one processor chip. , It has the effect of reducing the area and power consumption than a single architecture type neural network processor or a simple CNN and RNN integrated structure processor by sharing a memory part, a data bus, and an external interface.