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Junction gate field-effect transistor (JFET) having source/drain and gate isolation regions

摘要

A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. The at least one gate region contacts one of the source and drain regions at an interface, and the at least one gate region is isolated from the other of the source and drain regions. A dielectric layer covers the interface while exposing portions of the gate region and the one of the source and drain regions.

著录项

  • 公开/公告号US10658477B2

    专利类型

  • 公开/公告日2020.05.19

    原文格式PDF

  • 申请/专利权人

    申请/专利号US15882796

  • 申请日2018.01.29

  • 分类号

  • 国家 US

  • 入库时间 2022-08-21 10:58:49

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