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Failure analysis device, failure analysis method, failure analysis program, teacher data creation device, teacher data creation method, and teacher data creation program

摘要

PROBLEM TO BE SOLVED: To provide a failure analysis device capable of accurately analyzing a cause of manufacturing failure. A defect analysis apparatus for analyzing a cause of manufacturing defects in a semiconductor wafer having a plurality of integrated circuits including a plurality of defective integrated circuits, the wafer map indicating positions of the plurality of defective integrated circuits on the semiconductor wafer. The Delaunay triangulation is performed on the point cloud data of a plurality of defective integrated circuits in the data, and the Delaunay diagram having each point data of the point cloud data as vertices is created. A vertex whose length is equal to or greater than a predetermined length is extracted, point data indicating the position of the defective integrated circuit corresponding to the extracted vertex is excluded from the wafer map data, and a correction unit that corrects the wafer map data, And an analysis unit that analyzes the cause of manufacturing defects of the semiconductor wafer using the corrected wafer map data. [Selection diagram] Figure 2

著录项

  • 公开/公告号JP2020088263A

    专利类型发明专利

  • 公开/公告日2020.06.04

    原文格式PDF

  • 申请/专利权人 富士通株式会社;

    申请/专利号JP2018223431

  • 发明设计人 新田 泉;

    申请日2018.11.29

  • 分类号

  • 国家 JP

  • 入库时间 2022-08-21 10:57:21

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