A memory comprising an array (200) of memory cells, the array including a plurality of columns, each memory cell in the array (200) of memory cells including a magnetic tunnel junction (MTJ) device (102) coupled to a dual-gate transistor (104), the dual-gate transistor (104) having a first gate (106) coupled to a word line (202, 204, 206) of a plurality of word lines and having a second gate (108) coupled to a write enable line (208, 210, 212) of a plurality of write enable lines; wherein at least one column of the plurality of columns is controllable by the write enable line (208, 210, 212) during a write operation, and wherein a read operation is operative to be performed by biasing the write enable line (208, 210, 212) and the word line (202, 204, 206) to enable a read current and not a write current through the MTJ device (102).
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