CIRCUIT DE VERROUILLAGE À FAIBLE ONDULATION POUR RÉDUIRE UN EFFET DE COURANT DE COURT-CIRCUIT

摘要

A latch circuit (300) includes an input stage (310), an amplifying stage (MN1, MN2, MP1, MP2) and a clock gating circuit (320). The input stage (310) is arranged for receiving at least a clock signal and a data control signal. The amplifying stage (MN1, MN2, MP1, MP2) is coupled to the input stage (310) and supplied by a supply voltage and a ground voltage, and is arranged for retaining a data value and outputting the data value according to the clock signal and the data control signal. The clock gating circuit (320) is coupled to the amplifying stage (MN1, MN2, MP1, MP2), and is arranged for avoiding a short-circuit current between the supply voltage and the ground voltage.