Procedure for the production of a semiconductor structure containing a ferro-electric material and a semiconductor structure comprising a ferro-electric transistor

摘要

A method comprising: providing a semiconductor structure comprising an area (102) for a logic transistor, an area (103) for the ferroelectric transistor and an area (104) for an input / output transistor; forming a first protective layer (107) over the semiconductor structure, the first protective layer (107) covering the area (102) for the logic transistor and the area (104) for the input / output transistor, at least a part of the area (103) for the ferroelectric transistor is not covered by the first protective layer (107); and after forming the first protective layer (107): depositing a dielectric (201) for a ferroelectric transistor over the semiconductor structure, and removing the dielectric (201) for the ferroelectric transistor and the first protective layer (107) from the region (102) for the Logic transistor and the area for the input / output transistor, depositing a second protective layer (301) over the semiconductor structure after removing the dielectric (201) for the ferroelectric transistor and the first protective layer (107) from the area (102) for the logic transistor and the region (104) for the input / output transistor; andremoving portions of the second protective layer (301) over the area (102) for the logic transistor and the area (104) for the input / output transistor, a portion of the second protective layer (301) covering the area (103) for the ferroelectric transistor, remains in the semiconductor structure; after removing portions of the second protective layer (301) over the area (102) for the logic transistor and the area (104) for the input / output transistor, forming one Dielectric (403) for an input / output transistor over the region (104) for the input / output transistor and forming a dielectric (501) for a logic transistor over at least the region (102) for the logic transistor; wherein the dielectric (501) for the logic transistor is removed from the area (103) for the ferroelectric transistor together with a portion of the second protective layer (301) over the area (103) for the ferroelectric transistor.