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Communication architectures for single-chip data routers.

机译:单芯片数据路由器的通信体系结构。

摘要

This dissertation presents a novel architectural technique for systolic architectures for applications which traditionally use high wire organizations in VLSI. Following a review of current VLSI research and VLSI models, this dissertation argues for a particular computational model (Chazelleu27s model) as being appropriate for todayu27s VLSI and ULSI technology. Systolic arrays are particularly suited for applications where only local interprocessor communication of data is required. In areas where non local data communication is predominant, the so called u22high wire organizationsu22 are traditionally used. Such networks include sorting arrays, interconnection arrays. Using Chazelleu27s model, an analysis of well known interconnection networks shows that u22inefficientu22 systolic arrays, for routing and for sorting, outperform, so far as asymptotic performance metrics are concerned, high wire organizations traditionally used for such applications. This dissertation then proposes a new systolic architecture using the novel design philosophy of locally long but globally short connections. This involves designing arrays using large, complex cells instead of fine grained cells. This is termed u22systolic architectures using cells of controllable complexityu22 since the latency and/or pipeline period requirement of a user determines the size and hence the interconnection complexity of the cells in a systolic array of complex cells. It turns out that many important application areas (e.g., interconnection networks, sorting networks and FFT) are suitable candidates for this approach. This class of architectures is well suited for ULSI implementation. An experiment in designing interconnection networks show that this concept of arrays using cells of controllable complexity is useful, even in current 1.2$mu$ VLSI technology.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses u26 Major Papers - Basement, West Bldg. / Call Number: Thesis1992 .P358. Source: Dissertation Abstracts International, Volume: 53-12, Section: B, page: 6471. Co-Supervisors: G. A. Jullien; D. Bandyopadhay. Thesis (Ph.D.)--University of Windsor (Canada), 1991.
机译:本文提出了一种用于脉动体系结构的新颖体系结构技术,该体系结构用于传统上在VLSI中使用高布线组织的应用。在回顾了当前的VLSI研究和VLSI模型之后,本文提出了一种适用于当今VLSI和ULSI技术的特定计算模型(Chazelle模型)。脉动阵列特别适用于仅需要本地处理器间数据通信的应用。在非本地数据通信占主导地位的地区,传统上使用所谓的“高线组织”。这样的网络包括排序阵列,互连阵列。使用Chazelle模型,对著名的互连网络的分析表明,就渐近性能指标而言,用于路由和排序的收缩阵列的性能优于传统上用于此类应用的高线组织。然后,本文提出了一种新颖的脉动体系结构,它采用了局部长而全局短的连接的新颖设计理念。这涉及使用大型复杂单元而不是细粒度单元来设计阵列。由于用户的等待时间和/或流水线周期要求决定了复杂单元的脉动阵列中单元的大小以及互连的复杂性,因此这被称为使用复杂度可控制的单元的脉动体系结构。事实证明,许多重要的应用领域(例如,互连网络,分类网络和FFT)都适合此方法。此类体系结构非常适合于ULSI实现。设计互连网络的实验表明,即使在当前的1.2μmVLSI技术中,使用可控制复杂性单元的阵列的概念也是有用的。电气和计算机工程系。莱迪图书馆的纸质副本:论文主要论文-西楼地下室。 /电话号码:Thesis1992 .P358。资料来源:国际学位论文摘要,第53卷至第12卷,第B部分,第6471页。联合主管:G. A. Jullien; D.班迪帕德论文(博士学位)-温莎大学(加拿大),1991。

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    Panneerselvam Gopal.;

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  • 年度 1991
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