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Núcleo IP de uma bridge ethernet baseado em lógica reconfigurável e processador SoftCore

机译:基于可重配置逻辑和SoftCore处理器的以太网桥的IP内核

摘要

The constant increase of density in today´s programmable logic devices (FPGA’s), together with the lowering of prices of these integrated circuits, has been making possible the implementation of complex systems which, some time ago, would require dedicated integrated circuits. In designs where an FPGA is already in use, it is even easier to justify the integration of new functionalities to the programmable logic project, as the costs involving the software and hardware development tools have already been used. This work implements an Ethernet bridge using a system composed by softprocessor, where the functions related to the packet classification and forwarding are executed in software, what makes the system far more versatile and friendly to implementation changes in the future, as well as easy maintenance. Besides the softprocessor, implemented in VHDL there are the media access controller (MAC) and an HDLC controller, which is used as the connection point between the local and remote bridges. The prototyping of the system, to evaluate the performance, has been done using the software tools and development boards from Xilinx, since they were easily accessible and offer the MicroBlaze softprocessor IP core, a 32 bit RICS processor with harvard architecture. The performance analysis of the system, done with use of software tools like Iperf and hardware tools like SmartBits, has shown that the bridge was fast enough to handle small packets at a rate over 1Mbps. For larger packets, the performance was close to the 2Mbps, which represent the maximum typical rate where this bridge will be inserted in the real applications. Due to its extremely versatile nature, having been implemented using programmable logic and software functions, the system can handle the inclusion of new features in future activities, such as packet filtering, virtual LAN’s and the Spanning Tree Protocol. Besides these new software functionalities, new hardware modules can also be inserted, be it either to implement new features, such as the increase in the number of WAN interfaces, or to simply optimize existing logic blocks.
机译:当今可编程逻辑器件(FPGA)密度的不断提高,以及这些集成电路价格的降低,使得实现复杂的系统成为可能,而复杂的系统有时需要专用集成电路。在已经使用FPGA的设计中,由于已经使用了涉及软件和硬件开发工具的成本,因此更容易证明将新功能集成到可编程逻辑项目中是合理的。这项工作使用由软件处理器组成的系统来实现以太网桥,其中与数据包分类和转发有关的功能在软件中执行,这使得该系统更加通用,对将来的实现更改更为友好,并且易于维护。除了VHDL中实现的软件处理器之外,还有媒体访问控制器(MAC)和HDLC控制器,它们用作本地和远程网桥之间的连接点。该系统的原型用来评估性能,是使用Xilinx的软件工具和开发板完成的,因为它们易于访问,并提供MicroBlaze软处理器IP内核,这是一种具有哈佛架构的32位RICS处理器。使用Iperf等软件工具和SmartBits等硬件工具对系统进行的性能分析表明,该网桥的速度足以以1Mbps以上的速率处理小数据包。对于较大的数据包,性能接近2Mbps,这代表将在实际应用中插入此网桥的最大典型速率。由于其用途广泛,已使用可编程逻辑和软件功能实现,因此该系统可以处理将来活动中包含的新功能,例如数据包过滤,虚拟LAN和生成树协议。除了这些新的软件功能之外,还可以插入新的硬件模块,以实现新功能(例如,增加WAN接口的数量)或仅优化现有逻辑块。

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