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Research and design of high-speed advanced analogue front-ends for fibre-optic transmission systems

机译:光纤传输系统高速先进模拟前端的研究与设计

摘要

In the last decade, we have witnessed the emergence of large, warehouse-scale data centres which have enabled new internet-based software applications such as cloud computing, search engines, social media, e-government etc. Such data centres consist of large collections of servers interconnected using short-reach (reach up to a few hundred meters) optical interconnect. Today, transceivers for these applications achieve up to 100Gb/s by multiplexing 10x 10Gb/s or 4x 25Gb/s channels. In the near future however, data centre operators have expressed a need for optical links which can support 400Gb/s up to 1Tb/s. The crucial challenge is to achieve this in the same footprint (same transceiver module) and with similar power consumption as today’s technology. Straightforward scaling of the currently used space or wavelength division multiplexing may be difficult to achieve: indeed a 1Tb/s transceiver would require integration of 40 VCSELs (vertical cavity surface emitting laser diode, widely used for short‐reach optical interconnect), 40 photodiodes and the electronics operating at 25Gb/s in the same module as today’s 100Gb/s transceiver. Pushing the bit rate on such links beyond today’s commercially available 100Gb/s/fibre will require new generations of VCSELs and their driver and receiver electronics. This work looks into a number of state‐of-the-art technologies and investigates their performance restraints and recommends different set of designs, specifically targeting multilevel modulation formats. Several methods to extend the bandwidth using deep submicron (65nm and 28nm) CMOS technology are explored in this work, while also maintaining a focus upon reducing power consumption and chip area. The techniques used were pre-emphasis in rising and falling edges of the signal and bandwidth extensions by inductive peaking and different local feedback techniques. These techniques have been applied to a transmitter and receiver developed for advanced modulation formats such as PAM-4 (4 level pulse amplitude modulation). Such modulation format can increase the throughput per individual channel, which helps to overcome the challenges mentioned above to realize 400Gb/s to 1Tb/s transceivers.
机译:在过去的十年中,我们目睹了大型仓库级数据中心的出现,这些数据中心启用了新的基于Internet的软件应用程序,例如云计算,搜索引擎,社交媒体,电子政务等。此类数据中心由大量馆藏组成使用短距离(可达几百米)光学互连互连的服务器数量。如今,用于这些应用的收发器通过多路复用10x 10Gb / s或4x 25Gb / s通道达到高达100Gb / s的速度。但是,在不久的将来,数据中心运营商已经表示需要可支持高达1Tb / s的400Gb / s的光链路。关键的挑战是要在与当今技术相同的占地面积(相同的收发器模块)中实现相同的功耗。目前使用的空间或波分复用的直接缩放可能难以实现:实际上,一个1Tb / s收发器将需要集成40个VCSEL(垂直腔表面发射激光二极管,广泛用于短距离光学互连),40个光电二极管和与当今100Gb / s收发器相同的模块中的电子设备以25Gb / s的速度运行。要使此类链路的比特率超过当今的商用100Gb / s /光纤,将需要新一代VCSEL及其驱动器和接收器电子设备。这项工作研究了许多最新技术,并研究了它们的性能限制,并建议了不同的设计方案,特别是针对多级调制格式的设计方案。在这项工作中,探索了几种使用深亚微米(65nm和28nm)CMOS技术扩展带宽的方法,同时也将重点放在降低功耗和芯片面积上。所使用的技术是通过感应峰值和不同的局部反馈技术来预强调信号的上升沿和下降沿以及带宽扩展。这些技术已应用于为高级调制格式(例如PAM-4(4级脉冲幅度调制))开发的发射机和接收机。这种调制格式可以增加每个单独通道的吞吐量,这有助于克服上述提到的实现400Gb / s至1Tb / s收发器的挑战。

著录项

  • 作者

    Quadir Nasir Abdul;

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  • 年度 2014
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  • 原文格式 PDF
  • 正文语种 en
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