The Pattern Articulation Unit of Illiac III: Simulation: Part I. Iterative Array, Transfer Memory and Boole Control

摘要

The Pattern Articulation Unit is simulated in three parts: control, Iterative Array (IA) and Transfer Memory (TM), all written in PL/1. The Iterative Array is a 1024 module parallel processor, and the Transfer Memory is a 48 x 1024-bit read/write memory. In the simulation program, both the IA and TM are defined as three-dimensional arrays, each element in the array being one bit long (bit attribution). As the borders of the IA function differently from the interior, they are defined separately. (Author)