Generating Layouts for Random Logic: Cell Generation Schemes

摘要

Starting from a boolean expression, the process of generating a linear transistor array, also called a cell, is described for NMOS. This result is used to obtain a practical method for generating CMOS cells. The adopted Depth First Search provides a clearly structured basic algorithm consisting of modules that can easily be adjusted or extended. In this way the cell generator may be tuned to calculate solutions in minimum cpu-time or solutions that need minimum area, or even have fitting dimensions regarding their surrounding cells. A data structure that makes it possible to modify the structure of the network without changing the implemented logic function is presented. This approach is then applied to the basic algorithm.