Lazy Release Consistency for Hardware-Coherent Multiprocessors

摘要

Release consistency is a widely accepted memory model for distributed sharedmemory systems. It provides significant opportunities for a coherence protocol to improve performance by delaying and buffering coherence operations. Different protocol implementations exploit these opportunities to different extents. Eager release consistency represents the state of the art for hardware-coherent multiprocessors, while lazy release consistency has been shown to provide better performance for software distributed shared memory (DSM). Several of the optimizations performed by lazy protocols have the potential to improve the performance of hardware-coherent multiprocessors, but their complexity has precluded a hardware implementation. With the advent of programmable protocol processors it may become possible to use them after all. We present and evaluate a lazy release-consistent protocol suitable for machines with dedicated protocol processors. This protocol admits multiple concurrent writers, sends write notices concurrently with omputation, and delays invalidations until acquire operations. We also consider a lazier protocol that delays sending write notices until release operations. Our results indicate that the first protocol outperforms eager release consistency by as much as 20% across a variety of applications. The lazier protocol, on the other hand, is unable to recoup its high synchronization overhead. This represents a qualitative shift from the DSM world, where lazier protocols always yield performance improvements. We also study protocol performance under a variety of architectural settings and show that the performance gap between lazy and eager implementations of release consistency will increase on future machines. Based on our results, we conclude that machines with flexible hardware support for coherence should use protocols based on lazy release consistency, but in a less 'aggressively lazy' form than is appropriate for DSM.