FINAL TECHNICAL SUMMARY REPORT ADVANCED TELEMETRY SYSTEM WITH ADAPTIVE CAPABILITY, PHASE V AND PHASE VII

摘要

The relative complexity of mechanizing the logic functions for the ZFN and ZVA/FVA algorithms is indicated in Table 1-1. The module counts for the ZFN algorithm were derived from the experimental flight units, produced in Phase VI, but modified to reflect improvements related to the reference memory design end to take advantage of the use of low power DTZ integrated circuits now available. Module counts for the hybrid ZVA/FVA system were from n const of logic functions in the ZVA/FVA system breadboard. Component counts;related directly with driving and sensing of outputs from the magnetic storage elements, for the reference and buffer memories are not included in Table 1-1. The ZVA and FVA algorithms have the same buffer memory require¬ments as the ZFN algorithm. However, the reference memory for the ZVA/FVA system requires 36 DRO and 8 BUBO bits per word compared to 11 DRO and 7 EURO bits for the up-dated ZFN system. She increases complexity of the reference memory in the ZVA/FVA is in the added bit arrays of storage elements, inhibit drivers, and sense amplifiers. The word capacity and associated address circuitry would be the sane for ZFN and ZVA/FVA systems.