Gate Selection for Multiple-Valued Logic Systems

摘要

With the development of the integrated circuit and growth of microcircuitry, the use of multi-state devices and multi-valued logic functions in the place of presently used binary systems is becoming increasingly more feasible. A method for N-valued system design that optimizes the cost, however, has thus far not been developed. This thesis presents a choice of a four-gate set which will reduce the average cost of implementation for a truth table. The set is composed of the minimum (AND) gate, the maximum (OR) gate, the modulo-N add gate, and a NOT gate specially defined for multi-valued systems. The choice is a compromise to require the manufacture of only four different gates, and yet the various combinations of the four gates can offer enough flexibility to cover output requirements with a reduced implementation cost. (Author)