Development of a Hierarchical,Dynamically Reconfigurable Input/Output Network.

摘要

This thesis traces the development of the hierarchical, dynamically reconfigurable, input/output network which has been constructed at the Draper Laboratory. It presents a summary of the design procedures used in determining the network architecture, communication methods, message formats, and overall topology. Further, it describes both the hardware and software features that have been implemented in the network's microprocessor-based nodes. In addition, the centrally located software algorithms developed to configure, repair, and monitor the network have been extensively discussed. Finally, the thesis also includes a reliability analysis of the network in a typical application, and a performance evaluation of the effectiveness of the configuration and control programs.