Declarative Descriptions for VLSI (Very Large Scale Integration) Generators

摘要

This thesis presents a declarative generator model which can be used to guide the generation of a circuit in VLSI design. The descriptions in the model provide four equivalent representations of a circuit. They are the layout description, the mixed mode description, the schematic description, and the functional description. Each serves a unique purpose in the VLSI design process. They are correlated through corresponding components. These descriptions are declarative, abstract, robust, and structured in a hierarchical manner. The syntax and semantics of the declarative descriptions are introduced. Their applications are illustrated by examples. The declarative descriptions are shown to greatly facilitate the VLSI design process and serve as a comprehensive tool that documents the designer's ideas as well as the complexities of a circuit. (Author)