Optimization of One-Bit Full Adders Embedded in Regular Structures

摘要

This reprint studies the problem of optimizing the transistor sizes in the one-bit nMOS full adder either isolated or embedded in a regular array. A local optimization method that we call the critical-path optimization method is developed. In this method, two parameters at a time are changed along the critical path until a locally optimal choice of transistor sizes is found. The critical-path optimization method uses the Berkeley VLSI tools and the hierarchical layout language ALLENDE developed at Princeton. First, we optimize the isolate one-bit full adder implemented in three ways: as a PLA, data selector, and with random logic. The details of the critical-path optimization method and power-time tradeoff curves are illustrated here. Second, we optimize the one-bit full adder embedded in a simple array multiplier. The entire 3 x 3, 4 x 4, 8 x 8, and 10 x 10 multipliers are optimized and their local optima are compared. (KR)