Locality-Based Multiprocessor Cache Interference Model.

摘要

Keeping data consistent in cache-coherent multiprocessors often requires the invalidation of cached blocks and results in higher miss rates. The increase in the cache miss rate due to invalidations is related to the number of processors and to the level of sharing. Analytically modeling this increase is important for the accurate performance evaluation of cache-based multiprocessors. Previous modeling efforts assumed a uniform probability of access to shared blocks. However, applications that we have studied show significant temporal locality of access to shared blocks, which substantially alters the magnitude of sharing related misses. This paper develops a multiprocessor cache interference model using temporal locality information measured from address traces of parallel applications. The model is very simple and yields reasonable predictions. Keywords: Cache coherence; Shared-memory multiprocessors, Processor locality; Multiprocessor performance evaluation. (aw)