Implementation of FFT and Pulse Compression Routines on the SPT Frequency Domain Array Processor.

摘要

The Frequency Domain Array Processor (FDAP) is a VME compatible circuit board built by Signal Processing Technologies (SPT). The FDAP can process integer data arrays containing up to 8192 (32 bit) complex words or 1684 (16 bit) real words. It is capable of 400 Million Operations Per Second (MOPS) with a maximum Input/Output (I/O) rate of four billion bits per second. It also has a double buffered memory architecture permitting I/O transfers to occur in parallel with data processing. The FDAP can be hosted by an IBM PC/AT-compatible computer using a bus adaptor interface available from BIT3 Computer Corp. The FDAP board is based upon SPT's DASP/PAC chip set. This chip set and the varios system architectures which can be built around it are reviewed. The FDAP board and its associated development system are also reviewed. The ease of implementation of typical radar signal processing functions on the FDAP board are then examined. Fast Fourier Transform and pulse compression routines are implemented via a supplied user interface as well as a high level language (C). The results are examined and comments on the FDAP and its associated system development tools are made.