We have demonstrated a digital receiver performing direct digitization of radio-frequency signals over a wide frequency range from kilohertz to gigahertz. The complete system, consisting of a cryopackaged superconductor all-digital receiver (ADR) chip followed by room-temperature interface electronics and a field programmable gate array (FPGA) based post-processing module, has been developed. The ADR chip comprises a low-pass analog-to-digital converter (ADC) delta modulator with phase modulation-demodulation architecture together with digital in-phase and quadrature mixer and a pair of digital decimation filters. The chip is fabricated using a 4.5 kA cm~(-2) process and is cryopackaged using a commercial-off-the-shelf cryocooler. Experimental results in HF, VHF, UHF and L bands and their analysis, proving consistent operation of the cryopackaged ADR chip up to 24.32 GHz clock frequency, are presented and discussed.
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机译:我们已经展示了一种数字接收器,可以在从几千赫兹到几千赫兹的宽频率范围内对射频信号进行直接数字化。已经开发了完整的系统,该系统由低温封装的超导体全数字接收器(ADR)芯片,室温接口电子器件和基于现场可编程门阵列(FPGA)的后处理模块组成。该ADR芯片包括一个具有相位调制-解调架构的低通模数转换器(ADC)增量调制器,以及数字同相和正交混频器以及一对数字抽取滤波器。该芯片采用4.5 kA cm〜(-2)的工艺制造,并使用现成的商用低温冷却器进行低温封装。提出并讨论了在HF,VHF,UHF和L频段的实验结果及其分析,证明了低温封装的ADR芯片在高达24.32 GHz时钟频率下的稳定运行。
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