A stochastic computing framework for a Markov Chain Monte Carlo (MCMC) multiple-input-multiple-output (MIMO) detector is proposed, in which the arithmetic operations are implemented by simple logic structures. Specifically, we introduce two new techniques, namely a sliding window generator (SWG) and a log-likelihood ratio based updating method (LUM), to achieve an efficient design. The SWG utilizes the variance in stochastic computations to increase the transition probability of the MCMC detector, while the LUM reduces the hardware cost. As a case study, we design a fully-parallel stochastic MCMC detector for a 4 × 4 16-QAM MIMO system using 130 nm CMOS technology. The proposed detector achieves a throughput of 1.5 Gbps with only a 0.2 dB performance loss compared to a traditional floating-point detection method. Our design has a 30 better ratio of gate count to scaled throughput compared to other recent MIMO detectors.
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