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Partial-response maximum-likelihood core development for a CD/DVD controller integrated circuit

机译:CD/DVD控制器集成电路的部分响应最大似然磁芯开发

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摘要

A new PRML architecture is presented to demonstrate its superiority over the conventional analog channel in a DVD system. In this new architecture, the robustness to the baseline disturbance in the readback signal is emphasized in developing the algorithms for the PLL, digital gain control, asymmetry control, adaptive FIR filter, and Viterbi detector and post processor. In addition, a method of modeling the asymmetrical readback signal is discussed. A new algorithm for the digital PLL is described which does not require the oversampling. A simple method is presented to reduce the asymmetry in the ADC samples. To further improve the sensitivity to the baseline wandering, a Viterbi detector is designed using the difference metric approach and followed by a post processor, which corrects the baseline related errors from the VD. A test chip is fabricated using 0.35 μm CMOS technology to demonstrate the performance of the proposed architecture.
机译:提出了一种新的PRML架构,以证明其优于DVD系统中的传统模拟通道。在这种新架构中,在开发PLL、数字增益控制、不对称控制、自适应FIR滤波器以及Viterbi检波器和后处理器的算法时,强调了对回读信号基线干扰的鲁棒性。此外,还讨论了一种对非对称回读信号进行建模的方法。描述了一种不需要过采样的数字PLL的新算法。提出了一种减少ADC样品不对称性的简单方法。为了进一步提高对基线漂移的灵敏度,使用差分度量方法设计了Viterbi检测器,然后使用后处理器来校正VD的基线相关误差。使用0.35 μm CMOS技术制造了测试芯片,以演示所提架构的性能。

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