We devised an efficient architecture of deblocking filter and implemented the circuit with 15,400 logic gates and a 160 x 32 dual-port SRAM using 0.25 μm standard cell technology. This circuit can process 88 image frames with 1,280 x 720 pixels per second at 166 MHz. Our circuit requires smaller number of accesses to the external memory than other approaches and hence causes less bus traffic in the SoC design platform.
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机译:我们设计了一种高效的解块滤波器架构,并使用 0.25 μm 标准单元技术实现了具有 15,400 个逻辑门和 160 x 32 双端口 SRAM 的电路。该电路可以在166 MHz频率下以每秒1,280 x 720像素的速度处理88个图像帧。与其他方法相比,我们的电路需要更少的外部存储器访问次数,因此在 SoC 设计平台中导致的总线流量更少。
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