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Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation

机译:用于深亚微米延迟测试和时序验证的关键路径选择

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摘要

Critical path selection is an indispensable step for AC delay test and timing validation. Traditionally, this step relies on the construction of a set of worse-case paths based upon discrete timing models. However, the assumption of discrete timing models can be invalidated by timing defects and process variation in the deep sub-micron domain, which are often continuous in nature. As a result, critical paths defined in a traditional timing analysis approach may not be truly critical in reality. In this paper, we propose using a statistical delay evaluation framework for estimating the quality of a path set. Based upon the new framework, we demonstrate how the traditional definition of a critical path set may deviate from the true critical path set in the deep sub-micron domain. To remedy the problem, we discuss improvements to the existing path selection strategies by including new objectives. We then compare statistical approaches with traditional approaches based upon experimental analysis of both defect-free and defect-injected cases.
机译:关键路径选择是交流延迟测试和时序验证不可或缺的步骤。传统上,此步骤依赖于基于离散时序模型构建一组最坏情况的路径。然而,离散时序模型的假设可能会因深亚微米域中的时序缺陷和工艺变化而失效,这些缺陷和过程变化通常是连续的。因此,在传统的时序分析方法中定义的关键路径在现实中可能并不真正关键。在本文中,我们建议使用统计延迟评估框架来估计路径集的质量。基于新框架,我们展示了关键路径集的传统定义如何偏离深亚微米域中真正的关键路径集。为了解决这个问题,我们讨论了通过纳入新目标来改进现有的路径选择策略。然后,我们将统计方法与基于无缺陷和缺陷注入病例的实验分析的传统方法进行比较。

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