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Statistical Gate Delay Model for Multiple Input Switching

机译:多路输入切换的统计门延迟模型

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摘要

In this paper, we propose a calculation method of gate delay for SSTA (Statistical Static Timing Analysis) considering MIS (Multiple Input Switching). In SSTA, statistical maximum/minimum operation is necessary to calculate the latest/fastest arrival time of multiple input gate. Most SSTA approaches calculate the distribution in the latest/fastest arrival time under SIS (Single Input Switching assumption), resulting in ignoring the effect of MIS on the gate delay and the output transition time. MIS occurs when multiple inputs of a gate switch nearly simultaneously. Thus, ignoring MIS causes error in the statistical maximum/minimum operation in SSTA. We propose a statistical gate delay model considering MIS. We verify the proposed method by SPICE based Monte Carlo simulations. Experimental results show that the neglect of MIS effect leads to 80 error in worst case. The error of the proposed method is less than 20.
机译:本文提出了一种考虑MIS(Multiple Input Switching)的SSTA(Statistical Static Timing Analysis)门延迟计算方法。在SSTA中,统计最大/最小运算是计算多个输入门的最晚/最快到达时间所必需的。大多数SSTA方法在SIS(Single Input Switching assumption,单输入切换假设)下计算最晚/最快到达时间的分布,导致忽略了MIS对栅极延迟和输出转换时间的影响。当栅极开关的多个输入几乎同时发生时,就会发生 MIS。因此,忽略 MIS 会导致 SSTA 中统计最大值/最小值运算出现错误。我们提出了一个考虑MIS的统计门延迟模型。我们通过基于SPICE的蒙特卡罗模拟验证了所提出的方法。实验结果表明,忽视MIS效应在最坏情况下会导致80%的误差。所提方法的误差小于20%。

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