We developed a process technology to remove parasitic capacitance around gate electrode originated in interconnecting layer of circuits. This process enabled us to increase the operating speed of integrated circuit, and we reported 90 GHz operation of a static T-FF circuit. We evaluated S-parameter precisely and confirmed the effect of reducing parasitic capacitance. This process technology has potential to further improve cutoff frequency, f{sub}T, by further reducing the length of the gate electrode.
展开▼
