A clock synchronization circuit is described which can monitor and remove positive and negative errors less than 500 ms. An additional logic circuit increases the correction range to #xb1; 30 seconds and is applicable to clocks which accumulate larger errors. The synchronization can work with several reference time signals or with a master clock directly. The circuit is inherently capable of providing a synchronization accuracy of about a microsecond but is limited by the propagation errors where transmitted time signals are used.
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