Low voltage vertical Power MOSFETs employ the substrates doped by Arsenic (As) for low on-resistance issue. However, those substrates lead to un-uniformity breakdown problem for high voltage (HV) epitaxy (low concentration) caused by the out-doping phenomenon under processing. In this study, we use the antimony-doped (Sb) substrate to avoid this drawback for HV devices. However, devices fabricated with Sb-doped substrate show a higher source-drain turn on voltage (V{sub}(SD)) owing to a higher drain contact resistance, which increase power loss than the As doped devices under device switching. To lower the V{sub}(SD), we bake the devices with different temperature and time conditions and investigate the V{sub}(SD) characteristics. It is shown that the V{sub}(SD) can be reduced 35 at 350℃ with 6 hours conditions.
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