Design of sfl2vl: SFL to Verilog Converter Based on an LR-Parser

摘要

This paper presents the implementation of sfl2vl, a new free tool for SFL to Verilog conversion. Also this paper will discuss the performance of the conversion and the logic simulation of the sfl2vl+Icarus Verilog (free-ware compiler) versus PARTHENON with some MPU designs.