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首页> 外文期刊>電子情報通信学会技術研究報告. シリコン材料·デバイス. Silicon Devices and Materials >Quantitative Evaluation of Interface Traps in a Nanometer-Thick SiGe/Si Heterostructure in Hetero MOS Devices
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Quantitative Evaluation of Interface Traps in a Nanometer-Thick SiGe/Si Heterostructure in Hetero MOS Devices

机译:Quantitative Evaluation of Interface Traps in a Nanometer-Thick SiGe/Si Heterostructure in Hetero MOS Devices

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摘要

Recently-established low-temperature charge pumping (LTCP) technique is described, which is effective to quantitatively evaluate the interface trap density in nanometer-thick SiGe/Si heterostructures introduced in the channel region of Si MOSFETs. Hot carrier degradation at the hetero-interface is also described. The width of the hot-carrier-damaged hetero-interface region was estimated from experimental measurements by investigating and understanding the low-temperature charge pumping characteristics, and a quantitative estimate of the density of locally-generated hetero-interface traps was made.
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