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Investigation of Gate Misalignment Effects in FinFETs

机译:Investigation of Gate Misalignment Effects in FinFETs

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摘要

Gate misalignment effects on electrical properties of FinFETs have been investigated with three-dimensional (3-D) mixed-mode simulator. A major trade-off between S/D series resistances and diffusion capacitances was induced by the gate misalignment. The influences of series resistances on short channel effects of few tens nanometer device are discussed in detail. A SOI FinFET and a body-tied FinFET were compared in terms of FO4 inverter delay to assess the gate misalignment effects on circuit performance as a whole. In the SOI FinFET, source series resistance is dominant factor in determining RC delay, while drain diffusion capacitance is more significant in the body-tied FinFET.
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