SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4 Gb DRAM Technologies

摘要

Recently, the recessed SiGe source and drain (SD) structure is widely applied for boosting the performance of pMOS transistor due to the enhanced hole mobility. In this study, the SiGe SD structure was embedded in the peripheral pMOS transistor of DRAM for the first time. We used about 20 at. of Ge contents for the SiGe SD layer and more than 40 of I{sub}(ON) improvement in the pMOS transistor was shown without any degradation of the peripheral nMOS transistor properties. The low sheet resistance of the SiGe layer and the contact resistance between metal and SiGe layer as well as the compressive stress in the channel region are believed to be the origin of the performance gain in the pMOS. It was also confirmed that the Si elevated SD structure after the SiGe SD formation reduced the performance enhancement in the pMOS, which was also shown in the simulated results.