In this paper, the guideline of tolerable threshold voltage (Vth) fluctuation of MOS Current Mode Logic (MCML) was presented by using HSPICE simulations. The dependence of bias offset voltage △V{sub}B, that is defined as (base voltage of output waveform) - (base voltage of input waveform), on Vth fluctuation of NMOS and PMOS was investigated. The tolerable Vth fluctuation of NMOS and PMOS that satisfies △V{sub}B≤50 mV and △V{sub}B≤100 mV in MCML inverter was shown, respectively. With using this proposed guideline of tolerable Vth fluctuation, we clarified that in order to improve the stability of MCML inverter, it is effective to suppress the Vth fluctuation of NMOS.
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