A Secure Scan Design Approach Using Extended de Bruijn Graph

摘要

Scan design makes digital circuits easily testable, however, it can also be exploited to be used for hacking the chip. This paper introduces a new secure scan design approach using extended de Bruijn graph, which aims to satisfy both testability and security of digital circuits. The approach is only to replace the original scan chains to modified scan registers called extended scan registers. This method requires very little area overhead and no performance overhead. Moreover, no additional keys and controller circuits outside of the scan chain are needed, thus making the scheme low-cost and efficient.