A Low-Jitter Delay-Locked Loop with Harmonic-Lock Prevention

摘要

A multiphase low-jitter delay-locked loop (DLL) with harmonic-lockprevention, targeted at a gigabit par- allel link interface, isdelineated. A three-input four-state dy- namic phase detector (PD) isproposed to obviate harmonic lock- ing. Employing a low-jitter delayelement and a new type of PD, the DLL is compact and feasible in itsnature. The DLL is de- signed using a 0.35 μm 2P4M CMOS process with3.3 V supply. Experimental results show that the circuit avoids falselocking.