In this report, a spec-design CAD is proposed as a new system which can freely generate a Verilog-HDL source file in the RTL stage. The HDL source is the design data of the circuit provided with functions and specification required by a user. A GUI is adopted as a user interface. The specification of the detail circuits generated is predicted beforehand and the information is fed back to a user immediately. Thereby, a setup of the design parameters is easily realized. This report focuses on the automatic generation of a DFT operation circuit as a simple example case of spec-design CAD and explains the structure of the parameter setup and its design data generation.
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