机译:High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme
Kyushu Institute of Technology, Iizuka-shi, 820-8502 Japan;
LIRMM, France;
SynTest, USAUniversity of Connecticut, USA;
power supply noise; test relaxation; X-filling; clock-gating; test compaction;