Analysis of reliability of low-temperature poly-Si TFTs with gate-overlapped LDD

摘要

We have discussed the degradation mechanism of the Low Temperature Poly-Si GOLD(Gate-Overlapped LDD) Structure TFTs using two-dimensional device simulator. We have calculated distributions of horizontal electric field, vertical field and free carriers for various doping conditions and various bias conditions systematically Hot carriers are generated far from the interface by the strong vertical electric field. Therefore, less hot electrons are injected into gate oxide. Therefore, the GOLD Structure is suitable for a high performance driving circuit.