Dual damascene aluminum for 1-Gbit DRAMs

摘要

An advanced four-level interconnect process with three levels of minimum pitch (0.35μm) dual damascene wiring is illustrated in this article. This novel process sequence is designed for a 1 -Gbit DRAM (0.175μm generation), and provides up to a10 saving in chip area over a conventional three-level scheme. The electromigration and stress-migration performance of dual damascene Al is far superior to that of traditional RIE Al, alleviating the need to use Cu for improved reliability.