We propose a technique of selecting seeds for the LFSR-based test pattern generators that are used in VLSI BIST. By setting the computed seed as an initial value, target fault coverage, for example 100, can be accomplished with minimum test length. We can also maximize fault coverage for a given test length. Our method can be used for both test-per-clock and test-per-scan BISTs. The procedure is based on vector representation over GF(2{sup}m) where m is the number of LFSR stages. The results show that the test lengths the selected seeds derive are about sixty percent shorter than those derived by conventionally selected seeds for a given fault coverage. We also show that the seeds obtained through this technique accomplish higher fault coverage than the conventional selection procedure. In term of the c7552 benchmark, taking a test-per scan architecture with a 20-bit LFSR as an example, the number of undetected faults can be decreased from 304 to 227 for 10,000 LFSR patterns using our proposed technique.
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