Compact, high-speed, low-power circuit techniques have been developed for square root circuits. MOSFETs with low-threshold voltage were used for critical paths and MOSFETs with high-threshold voltage were used in the non-critical path circuits, so that not only high-speed performance can be guaranteed, but also power dissipations in both an active-mode and a stand-by-mode can be reduced. A square root algorithm has been proposed to reduce both circuit volume and critical-path lengths. Square root circuits were designed using 0.13-μm CMOS technology to examine the effectiveness of new techniques in power reduction and speed improvement. SPICE simulation results showed that the maximum operating clock frequency of the 8-bit square root circuit was 620 MHz that was 1.67 times faster than that of the conventional 8-bit square root circuit. The active power of the 8-bit square root circuit at 200 MHz was 404.9 μW, a reduction to 60.9 of that of the conventional 8-bit square root circuit. The stand-by power of the 8-bit square root circuit was 107.9 nW, a reduction to 34.1 of that of the equivalent 8-bit circuit.
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