Aggressive scaling of complementary metal-oxide-semiconductor (CMOS) technology requires a high drive current to increase circuit speed. Both the gate capacitance Cg and carrier mobility μ can improve the drive current I{sub}d ～ C{sub}g μ. The ultrathin oxide, high-k dielectrics, and metal gate (to mitigate the poly-depletion effect) can increase gate capacitance. However, contamination issues, thermal budget, Fermi-level pinning, mobility degradation, and interfacial layer scalability delay the introduction of high-k dielectrics into industrial applications. The metal gate also suffers from work function availability, thermal budget, process compatibility, and contamination problems. The continuous scaling of the oxynitride films with increasing nitrogen content seems to be used down to the 22-nm technology node with an equivalent Oxide thickness of ～ 0.7 nm for low operation power applications 1. Mobility enhancement by strain, new materials such as Ge or SiGe channels, and new substrate orientation such as (110) and (111) offers alternative ways to increase drive current without suffering from gate current leakage due to gate dielectric scaling. The high mobility gives high source injection velocity into the quasi-ballistic transport channel of the advanced deca-nanometer devices 2, 3. For large devices, the mobility itself has more impact on the drive current 4.
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